The present invention relates in general to field effect transistors, and in particular to trench transistors and methods of their manufacture.
FIG. 1 is a simplified cross section of a portion of a conventional trench power metal-oxide-semiconductor field-effect transistor (MOSFET). A trench 10 has sidewalls 11 and bottom 17, and is lined with an electrically insulating material 12 that acts as a gate dielectric, and is filled with a conductive material 15, such as polysilicon, which forms the gate of the transistor. The trench, and hence the gate, extend from the surface of the silicon into the substrate down through a body region 22 and a drain region 16. In the example shown in FIG. 1, the body region 22 is a P-type region and the drain region 16 is an N-type region. Drain region 16 may be electrically contacted through the substrate of the device. N-type regions 14 adjacent to and on opposite sides of the trench 10 form the source electrode 18 of the transistor. An active channel region 20 is thus formed alongside of the trench between the N-type regions 14 of the source electrode 18 and the drain region 16.
An important parameter in a trench power MOSFET is the total gate charge. In some applications of conventional trench power MOSFETs, such as DC-DC converters, the lower the gate charge the better the efficiency of the overall design. One major component of the total gate charge is the charge required to supply what is known as the Miller capacitance, which is a parasitic capacitance that forms between the gate and the drain. The Miller capacitance is an effective increase of gate to drain capacitance effect due to a rising drain current in the MOSFET active state. As a result, a higher proportion of the total gate charge flows through the gate-drain capacitance, and the rate of the rise of the gate to drain voltage is reduced, causing negative feedback from the drain circuit to the gate circuit. Thus, an effective way to lower the gate charge is to reduce the Miller Capacitance. One method to decrease the Miller Capacitance is to increase the thickness of the gate dielectric. However a uniformly thicker gate dielectric layer requires higher gate charge which results in lower efficiency.
The present invention provides a trench metal oxide semiconductor field effect transistor (MOSFET) having a dielectric layer that is thicker in the bottom of the trench as compared to the dielectric layer on the sidewalls of the trench where the transistor channel is formed.
Accordingly, in one embodiment, the present invention provides for self-aligned local oxidation of silicon (LOCOS) in the bottom of a trench structure to produce a gate isolation structure including a dielectric layer formed on sidewalls and bottom of the trench, where the dielectric layer has a first thickness on the sidewalls and a second thickness on the bottom that is greater than the first thickness.
In another embodiment, the invention provides a trench field effect transistor formed on a silicon substrate, the trench transistor including a trench in a silicon substrate, a dielectric layer formed on sidewalls and bottom of the trench, the dielectric layer having a first thickness on the sidewalls and a second thickness on the bottom that is greater than the first thickness, and a gate conductive material substantially filling the trench.
In yet another embodiment, the invention provides a method of forming a gate dielectric layer of a trench field effect transistor including the steps of forming a trench extending into a silicon substrate, forming a first layer of a dielectric material along sidewalls and bottom of the trench, and forming a second layer of the dielectric material at the bottom of the trench, whereby, the bottom of the trench is lined with dielectric material with a greater thickness than the sidewalls of the trench. In an embodiment, the dielectric layer is formed with a self-aligned LOCOS process tuned to the specific geometries (trench depth, aspect ratio of sidewalls, etc) of the trench in the silicon substrate. In an alternative embodiment, the dielectric layer is formed with a hard mask provided over the silicon substrate proximate the trench.
The following detailed description and the accompanying drawings provide a better understanding of the nature and advantages of the trench transistor with a thick oxide at the bottom surface of the trench.